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tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 1/49 tentative toshiba mos digital integrated circuit silicon monolithic 2,097,152-words 4 banks 16-bits synchronous dynamic ram 4,194,304-words 4 banks 8-bits synchronous dynamic ram 8,388,608-words 4 banks 4-bits synchronous dynamic ram description tc59sm716as/asl is a cmos synchronous dynamic random access memory organized as 2,097,152-words 4 banks 16 bits and tc59sm708as/asl is organized as 4,194,304 words 4 banks 8 bits and tc59sm704as/asl is organized as 8,388,608 words 4 banks 4 bits. fully synchronous operations are referenced to the positive edges of clock input and can transfer data up to 143m words per second. these devices are controlled by commands setting. each bank are kept active so that dram core sense amplifiers can be used as a cache. the refresh functions, either auto refresh or self refresh are easy to use. by having a programmable mode register, the system can choose the most suitable modes which will maximize its performance. these devices are ideal for main memory in applications such as work-stations. features tc59sm716/m708/m704 parameter -70 -75 -80 t ck clock cycle time (min) 7 ns 7.5 ns 8 ns t ras active to precharge command period (min) 40 ns 45 ns 48 ns t ac access time from clk (max) 5.4 ns 5.4 ns 6 ns t rc ref/active to ref/active command period (min) 56 ns 65 ns 68 ns i cc1 operation current (max) (single bank) 80 ma 75 ma 70 ma i cc4 burst operation current (max) 100 ma 95 ma 90 ma i cc6 self-refresh current (max) 2 ma 2 ma 2 ma ? single power supply of 3.3 v 0.3 v ? up to 143 mhz clock frequency ? synchronous operations: all signals referenced to the positive edges of clock ? architecture: pipeline ? organization tc59sm716as/asl: 2,097,152 words 4 banks 16 bits tc59sm708as/asl: 4,194,304 words 4 banks 8 bits tc59sm704as/asl: 8,388,608 words 4 banks 4 bits ? programmable mode register ? auto refresh and self refresh ? burst length: 1, 2, 4, 8, full page ? cas latency: 2, 3 ? single write mode ? burst stop function ? byte data controlled by l-dqm, u-dqm (tc59sm716) ? 4k refresh cycles/64 ms ? interface: lvttl ? package tc59sm716as/asl: tsopii54-p-400-0.4f tc59sm708as/asl: tsopii54-p-400-0.4f tc59sm704as/asl: tsopii54-p-400-0.4f ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in g eneral can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibi lity of th e buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, a nd to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury o r damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in th e most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handlin g guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. ? the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfun ction o r failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energ y control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion cont rol instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this docume n t shall be made at the customer?s own risk. 000707 eba2
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 2/49 pin names pin assignment (top view) a0~a11 address bs0, bs1 bank select dq0~dq3 (tc59sm704) dq0~dq7 (tc59sm708) dq0~dq15 (tc59sm716) data input/output cs chip select ras row address strobe cas column address strobe we write enable dqm (tc59sm708/m704) udqm/ldqm (tc59sm716) output disable/write mask clk clock inputs cke clock enable v cc power ( + 3.3 v) v ss ground v ccq power ( + 3.3 v) (for dq buffer) v ssq ground (for dq buffer) nc no connection tc59sm716as/asl tc59sm708as/asl tc59sm704as/asl v ss nc v ssq nc dq3 v ccq nc nc v ssq nc dq2 v ccq nc v ss nc dqm clk cke nc a11 a9 a8 a7 a6 a5 a4 v ss 1 54 2 53 3 52 4 51 5 50 6 49 7 48 8 47 9 46 10 45 11 44 12 43 13 42 14 41 15 40 16 39 17 38 18 37 19 36 20 35 21 34 22 33 23 32 24 31 25 30 26 29 27 28 v ss dq7 v ssq nc dq6 v ccq nc dq5 v ssq nc dq4 v ccq nc v ss nc dqm clk cke nc a11 a9 a8 a7 a6 a5 a4 v ss v ss dq15 v ssq dq14 dq13 v ccq dq12 dq11 v ssq dq10 dq9 v ccq dq8 v ss nc udqm clk cke nc a11 a9 a8 a7 a6 a5 a4 v ss v cc dq0 v ccq dq1 dq2 v ssq dq3 dq4 v ccq dq5 dq6 v ssq dq7 v cc ldqm bs0 bs1 a10/ap a0 a1 a2 a3 v cc we cas ras cs v cc dq0 v ccq nc dq1 v ssq nc dq2 v ccq nc dq3 v ssq nc v cc nc bs0 bs1 a10/ap a0 a1 a2 a3 v cc we cas ras cs v cc nc v ccq nc dq0 v ssq nc nc v ccq nc dq1 v ssq nc v cc nc bs0 bs1 a10/ap a0 a1 a2 a3 v cc we cas ras cs ? the products described in this document are subject to the foreign exchange and foreign trade laws. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assume d b y toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from i ts use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation o r others. ? the information contained herein is subject to change without notice. 000707 eba2
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 3/49 block diagram note: the tc59sm704as/asl configuration is 4096 2048 4 of cell array with the dq pins numbered dq0~dq3. the tc59sm708as/asl configuration is 4096 1024 8 of cell array with the dq pins numbered dq0~dq7. the tc59sm716as/asl configuration is 4096 512 16 of cell array with the dq pins numbered dq0~dq15. cke a10 cell array bank #0 column decoder sense amplifier row decoder dq0~dqn cell array bank #3 column decoder sense amplifier row decoder cell array bank #2 column decoder sense amplifier row decoder mode register clock buffer clk cas we a0~a9 a11 bs0 bs1 dqm cs cell array bank #1 column decoder sense amplifier row decoder control signal generator ras command decoder address buffer refresh counter column counter data control circuit dq buffer
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 4/49 absolute maximum ratings symbol parameter rating unit notes v in , v out input, output voltage ? 0.3~v cc + 0.3 v 1 v cc , v ccq power supply voltage ? 0.3~4.6 v 1 t opr operating temperature 0~70 c 1 t stg storage temperature ? 55~150 c 1 t solder soldering temperature (10s) 260 c 1 p d power dissipation 1 w 1 i out short-circuit output current 50 ma 1 recommended dc operating conditions (ta = = = = 0~70c) symbol parameter min typ. max unit notes v cc power supply voltage 3 3.3 3.6 v 2 v ccq power supply voltage (for dq buffer) 3 3.3 3.6 v 2 v ih lvttl input high voltage 2 ? v cc + 0.3 v 2 v il lvttl input low voltage ? 0.3 ? 0.8 v 2 note: v ih (max) = v cc /v ccq + 1.2 v for pulse width 5 ns vil (min) = v ss /v ssq ? 1.2 v for pulse width 5 ns v ccq must be less than or equal to v cc . capacitance (v cc = = = = 3.3 v, f = = = = 1 mhz, ta = = = = 25c) symbol parameter min max unit input capacitance (a0~a11, bs0, bs1, cs , ras , cas , we , dqm * , cke) ? 4 pf c i input capacitance (clk) ? 5 pf c o input/output capacitance ? 6.5 pf note: these parameters are periodically sampled and not 100% tested. * ldqm, udqm (tc59sm716)
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 5/49 dc characteristics (v cc = = = = 3.3 v 0.3 v, ta = = = = 0~70c) -70 -75 -80 parameter symbol min max min max min max units notes operating current t ck = min, t rc = min active precharge command cycling without burst operation 1 bank operation i cc1 ? 80 ? 75 ? 70 3 cke = v ih i cc2 ? 40 ? 35 ? 30 3 standby current t ck = min, cs = v ih , v ih/l = v ih (min) / v il (max), bank: inactive state cke = v il (power down mode) i cc2p ? 1 ? 1 ? 1 3 cke = v ih i cc2s ? 10 ? 10 ? 10 standby current clk = v il , cs = v ih , v ih/l = v ih (min) / v il (max), bank: inactive state cke = v il (power down mode) i cc2ps ? 1 ? 1 ? 1 cke = v ih i cc3 ? 60 ? 55 ? 50 no operating current t ck = min, cs = v ih (min), bank: active state (4 banks) cke = v il (power down mode) i cc3p ? 10 ? 10 ? 10 burst operating current t ck = min read/write command cycling i cc4 ? 100 ? 95 ? 90 3, 4 auto refresh current t ck = min, t rc = min auto refresh command cycling i cc5 ? 170 ? 160 ? 150 3 standard products (aft) ? 2 ? 2 ? 2 ma self refresh current self refresh mode cke = 0.2 v low power version (aftl) i cc6 ? 800 ? 800 ? 800 a parameter symbol min max units notes input leakage current (0 v v in v cc , all other pins not under test = 0 v) i i (l) ? 5 5 a output leakage current (output disable, 0 v v out v ccq ) i o (l) ? 5 5 a lvttl output h level voltage (i out = ? 2 ma) v oh 2.4 ? v lvttl output l level voltage (i out = 2 ma) v ol ? 0.4 v
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 6/49 ac characteristics and operating conditions (v cc = = = = 3.3 v 0.3 v, ta = = = = 0~70c) (notes: 5, 6, 7) -70 -75 -80 symbol parameter min max min max min max units notes t rc ref/active to ref/active command period 56 ? 65 ? 68 ? t ras active to precharge command period 40 100000 45 100000 48 100000 t rcd active to read/write command delay time 15 ? 20 ? 20 ? ns t ccd read/write(a) to read/write(b) command period 1 ? 1 ? 1 ? cycle t rp precharge to active command period 15 ? 20 ? 20 ? t rrd active(a) to active(b) command period 15 ? 15 ? 20 ? 8 cl * = 2 7.5 ? 10 ? 10 ? t wr write-recovery time cl * = 3 7 ? 7.5 ? 8 ? cl * = 2 7.5 1000 10 1000 10 1000 t ck clk cycle time cl * = 3 7 1000 7.5 1000 8 1000 t ch clk high-level width 2.5 ? 2.5 ? 3 ? t cl clk low-level width 2.5 ? 2.5 ? 3 ? cl * = 2 ? 5.4 ? 6 ? 6 t ac access time from clk cl * = 3 ? 5.4 ? 5.4 ? 6 t oh output data hold time 3 ? 3 ? 3 ? t hz output data high-impedance time 3 7 3 7.5 3 8 7 t lz output data low-impedance time 0 ? 0 ? 0 ? t sb power-down mode entry time 0 7 0 7.5 0 8 t t transition time of clk (rise and fall) 0.5 10 0.5 10 0.5 10 t ds data-in set-up time 1.5 ? 1.5 ? 2 ? t dh data-in hold time 0.8 ? 0.8 ? 1 ? t as address set-up time 1.5 ? 1.5 ? 2 ? t ah address hold time 0.8 ? 0.8 ? 1 ? t cks cke set-up time 1.5 ? 1.5 ? 2 ? t ckh cke hold time 0.8 ? 0.8 ? 1 ? t cms command set-up time 1.5 ? 1.5 ? 2 ? t cmh command hold time 0.8 ? 0.8 ? 1 ? ns t ref refresh time ? 64 ? 64 ? 64 ms t rsc mode register set cycle time 14 ? 15 ? 16 ? ns 8 * cl means cas latency.
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 7/49 notes: (1) conditions outside the limits listed under ?absolute maximum ratings? may cause permanent damage to the device. (2) all voltages are referenced to v ss . (3) these parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of t ck and t rc . input signals are changed one time during t ck . (4) these parameters depend on the output loading. specified values are obtained with the output open. (5) power-up sequence is described in note 9. (6) ac test conditions output reference level 1.4 v, 1.4 v output load see diagram b below input signal levels 2.4 v, 0.4 v transition time (rise and fall) of input signals 2 ns input reference level 1.4 v (7) t hz defines the time at which the outputs achieve the open circuit condition and is not referenced to output voltage levels. ac test load (a) output 3.3 v 870 ? 50 pf 1.2 k ? ac test load (b) output 1.4 v 50 pf 50 ? z = 50 ?
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 8/49 (8) these parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number) (9) power-up sequence power-up must be performed in the following sequence. 1) power must be applied to v cc and v ccq (simultaneously) while all input signals are held in the ?nop? state. the clk signals must be started at the same time. 2) after power-up a pause of at least 200 s is required. it is required that dqm and cke signals must be held ?high? (v cc levels) to ensure that the dq output is in high-impedance state. 3) all banks must be precharged. 4) the mode register set command must be asserted to initialize the mode register. 5) a minimum of eight auto refresh dummy cycles is required to stabilize the internal circuitry of the device. the mode register set command can be invoked either before or after the auto refresh dummy cycles. (10) ac latency characteristics cke to clock disable (cke latency) 1 dqm to output in high-z (read dqm latency) 2 dqm to input data delay (write dqm latency) 0 write command to input data (write data latency) 0 cs to command input ( cs latency) 0 cl = 2 2 precharge to dq hi-z lead time cl = 3 3 cl = 2 1 precharge to last valid data out cl = 3 2 cl = 2 2 burst stop command to dq hi-z lead time cl = 3 3 cl = 2 1 burst stop command to last valid data out cl = 3 2 cycle cl = 2 bl + t rp read with autoprecharge command to active/ref command cl = 3 bl + t rp cl = 2 bl + t rp write with autoprecharge command to active/ref command cl = 3 bl + t rp cycle + ns
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 9/49 timing diagrams command input timing ras t ck t cl t ch t cms t cmh t t t t t cms t cmh t cms t cmh cs cas t cms t cmh we t cms t cmh a0~a11 bs0, bs1 t as t ah t ckh t cks t cks t ckh t cks t ckh cke clk v ih v il
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 10/49 read timing ras read cas latency cs cas we a0~a11 bs0, bs1 t ac dq clk t oh t hz t oh t ac burst length t lz output data valid output data valid read command
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 11/49 control timing of input data (tc59sm708/m704) control timing of output data (tc59sm708/m704) dq0~dq7 (dq0~dq3) * dqm cl k t cmh t cms t cmh t cms t dh t ds input data valid t dh t ds t dh t ds t dh t ds input data valid input data valid input data valid cke cl k t ckh t cks t ckh t cks t dh t ds input data valid t dh t ds t dh t ds t dh t ds input data valid input data valid input data valid (word mask) (clock mask) dq0~dq7 (dq0~dq3) * dq0~dq7 (dq0~dq3) * dqm cl k t cmh t cms t cmh t cms t ac t oh t ac t lz t ac t oh t hz t oh output data valid output data valid (output enable) (clock mask) output data valid t ac t oh dq0~dq7 (dq0~dq3) * cke cl k t ckh t cks t ckh t cks t oh t ac t oh t ac t oh output data valid output data valid t ac t ac t oh output data valid open * : tc59sm704
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 12/49 control timing of input data (tc59sm716) input data valid udqm ldqm clk t cmh t cms t cmh t cms t dh t ds input data valid t dh t ds t dh t ds t dh t ds input data valid input data valid input data valid t dh t ds input data valid t dh t ds t dh t ds t dh t ds input data valid input data valid (word mask) dq0~dq7 dq8~dq15 t cmh t cms t cmh t cms cke clk t ckh t cks t ckh t cks t dh t ds input data valid t dh t ds t dh t ds input data valid input data valid (clock mask) dq8~dq15 t dh t ds input data valid t dh t ds input data valid dq0~dq7 t dh t ds t dh t ds input data valid input data valid t dh t ds input data valid
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 13/49 control timing of output data (tc59sm716) cke clk t ckh t cks t ckh t cks t oh t ac t oh t ac output data valid output data valid (clock mask) dq0~dq7 output data valid t oh t oh t ac t ac t oh t oh output data valid output data valid dq8~dq15 output data valid t oh t oh t ac t ac t ac t ac udqm ldqm clk t cmh t cms t cmh t cms t lz t ac t oh t ac t oh t hz output data valid output data valid (output enable) dq0~dq7 t cmh t cms t cmh t cms output data valid t oh t ac t oh t ac t oh t ac output data valid dq8~dq15 output data valid t oh t ac t oh t ac output data valid t oh t hz open t lz t ac open
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 14/49 mode register set cycle a0 a1 a2 burst length a3 addressing mode a4 a5 a6 cas latency a7 0 (test mode) a8 0 reserved a9 write mode a10 0 a11 0 bs0 0 bs1 0 reserved burst length a2 a1 a0 sequential interleaved 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 1 0 1 1 1 0 reserved 1 1 1 full page reserved a3 addressing mode 0 sequential 1 interleaved a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 0 1 1 3 1 0 0 reserved a9 single write mode 0 burst read and burst write 1 burst read and single write ras t rsc t cms t cmh cs cas we a0~a11 bs0, bs1 clk t cms t cmh t cms t cmh t cms t cmh t as t ah set register data next command
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 15/49 operating timing example figure 1. interleaved bank read (burst length = 4, latency = 3) cas clk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras ras cs cas t rc t rc t rc we bs0 raa rbb rac rbd rae a10 raa caw cbx rac cay rbd cbz rae a0~a9, a11 dqm cke aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 dq t rrd t rrd t rrd t rrd active read active read active precharge precharge read read precharge active active bank#0 bank#2 bank#3 bank#1 idle bs1 t rp t ras t rp t ras t rp t ras t rcd t rcd t rcd t rcd t ac t ac t ac t ac rbb
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 16/49 figure 2. interleaved bank read (burst length = 4, latency = 3, auto precharge) cas clk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras ras cs cas t rc t rc t rc we bs0 raa rac rbd rae a10 raa cbx rac cay a0~a9, a11 dqm cke aw0 bx0 cy0 dq t rrd t rrd t rrd t rrd active read active read active read active active bank#0 bank#2 bank#3 bank#1 idle bs1 t rp t ras t rp t ras t rp t ras t rcd t rcd t rcd t rcd t ac t ac t ac t ac rbb caw rbb rbd cbz rae aw1 aw2 aw3 bx1 bx2 bx3 cy1 cy2 cy3 dz0 ap * read ap * ap * * : ap shows internal precharge start timing.
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 17/49 figure 3. interleaved bank read (burst length = 8, latency = 3) cas a0~a9, a11 clk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t ras ras cs cas t rc t rc t rc we bs0 raa rbb rac a10 raa cby dqm cke ax0 by0 by4 dq t rrd t rrd active read read active active bank#0 bank#2 bank#3 bank#1 idle bs1 t rp t ras t rp t rp t ras t rcd t rcd t rcd t ac t ac t ac cax rac caz ax1 ax2 ax3 by5 by6 by7 precharge rbb ax4 ax5 ax6 by1 cz0 precharge read precharge
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 18/49 figure 4. interleaved bank read (burst length = 8, latency = 3, auto precharge) cas clk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 cs t rc t ras ras cas t rc we bs0 raa rbb rac a10 raa cby a0~a9, a11 dqm cke ax0 by0 dq t rrd t rrd active read active active bank#0 bank#2 bank#3 bank#1 idle bs1 t ras t rp t rp t ras t rcd t rcd t rcd t ac t ac t ac cax rac caz ax1 ax2 ax3 by4 by5 by6 * : ap shows the internal precharge start timing. rbb ax4 ax5 ax6 by1 read ax7 cz0 ap * read ap *
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 19/49 figure 5. interleaved bank write (burst length = 8) clk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 cs t ras ras cas t rc we bs0 raa rbb rac a10 raa cby a0~a9, a11 dqm cke ax0 by0 dq t rrd t rrd active write active active bank#0 bank#2 bank#3 bank#1 idle bs1 t rp t rp t ras cax rac caz ax1 by4 by5 by6 rbb ax4 ax5 ax6 by1 ax7 precharge t rcd t rcd t rcd by2 by3 by7 cz0 cz1 cz2 write write precharge
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 20/49 figure 6. interleaved bank write (burst length = 8, auto precharge) clk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 cs t ras ras cas t rc we bs0 raa rbb rab a10 raa cby a0~a9, a11 dqm cke ax0 by0 dq t rrd t rrd active write active active bank#0 bank#2 bank#3 bank#1 idle bs1 t rp t rp t ras t rcd t rcd t rcd cax rac caz ax1 by4 by5 by6 rbb ax4 ax5 ax6 by1 ax7 by2 by3 by7 cz0 cz1 cz2 t ras ap * write ap * write * : ap shows the internal precharge start timing.
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 21/49 figure 7. page mode read (burst length = 4, latency = 3) cas clk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 ras cs cas t ras we bs0 raa a10 raa cay a0~a9, a11 dqm cke bx1 dq t rrd active active bank#0 bank#2 bank#3 bank#1 idle bs1 t rcd t rcd cal cbz bz0 rbb al0 al1 ay0 ay1 ay2 ap * * : ap shows the internal precharge start timing. t ccd t ccd t ccd t ras t rp t rp rbb cbx cam al2 al3 bx0 am0 am1 am2 bz1 bz2 bz3 t ac t ac t ac t ac t ac read read read read read precharge
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 22/49 figure 8. page mode read/write (burst length = 8, latency = 3) cas a0~a9, a11 ras cas clk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 t ras cs t rp cke bs1 dqm bs0 raa a10 t rcd raa cax cay dq active read precharge bank#0 bank#2 bank#3 bank#1 idle ax0 ax1 ax2 ax3 ax4 we ax5 ay0 ay1 ay2 ay3 ay4 q q q q q q d d d d d t wr t ac note): see figure 17, 20 write 22
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 23/49 figure 9. auto precharge read (burst length = 4, latency = 3) cas clk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc cs t rc cke bs1 dqm ras cas bs0 t rcd raa a0~a9, a11 dq active read bank#0 bank#2 bank#3 bank#1 idle we aw0 aw1 aw2 aw3 t ac cax bx0 bx1 bx2 bx3 t ac raa caw rab rab active read ap * * : ap shows the internal precharge start timing. note): see figure 15 ap * t rcd t rp t ras t ras t rp a10
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 24/49 figure 10. auto precharge write (burst length = 4) a0~a9, a11 clk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 cs t rc cke bs1 dqm ras cas bs0 a10 t rcd raa dq active write bank#0 bank#2 bank#3 bank#1 idle we aw0 aw1 aw2 aw3 raa caw rab rab ap * * : ap shows the internal precharge start timing. note): see figure 16 ap * t rcd t rp t ras t ras cax rac rac bx0 bx2 bx3 bx1 active write active t rc t rp
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 25/49 figure 11. auto refresh cycle clk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc cs ras cas bs0, bs1 we cke dqm a10 a0~a9, a11 dq all banks precharge auto refresh auto refresh (arbitrary cycle) t rp t rc
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 26/49 figure 12. self refresh cycle clk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 cs ras cas bs0, bs1 we cke dqm a10 a0~a9, a11 dq all banks precharge self refresh entry arbitrary cycle t cks t sb t cks no operation cycle t rc t cks t rp self refresh exit
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 27/49 figure 13. power down mode a0~a9, a11 clk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 cs cke dqm ras cas bs a10 raa dq active we raa caa note): the power down mode is invoked by asserting cke ?low?. all input/output buffers (except the cke buffer) are turned off in power down mode. when cke goes high, the no-operation command input must be at next clk rising edge and cke should be set high at least 1clk + t cks at power down mode exit. active ax0 ax2 ax1 ax3 cax raa raa nop precharge & power down mode entry nop t cks t sb t cks power down mode exit t cks t sb t cks power down mode entry power down mode exit
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 28/49 figure 14. burst read and single write (burst length = 4, latency = 3) cas a0~a9, a11 ras clk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 cs t rcd cke bs1 dqm bs0 rba a10 rba cbv cbw dq av0 av1 av2 av3 we az0 az1 az2 az3 q q q q t ac cas cbx cby cbz t ac aw0 ax0 ay0 q q q d d d bank#0 bank#2 bank#3 bank#1 idle active read read single write q
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 29/49 pin functions clock input: clk the clk input is used as the reference for sdram operations. operations are synchronized to the positive edges of clk. clock enable: cke the cke input is used to suspend the internal clk. when the cke signal is asserted ?low?, the internal clk is suspended and output data is held intact while cke is asserted ?low?. when the device is not running a burst cycle, the cke input controls the entry to the power down and self refresh modes. when the self refresh command is issued, the device must be in the idle state. bank select: bs0, bs1 the tc59sm716as/asl, tc59sm708as/asl and the tc59sm704as/asl are organized as four-bank memory cell arrays. the bs0, bs1 inputs are latched at the time of assertion of the operation commands and selects the bank to be used for the operation. bs0 bs1 0 0 bank#0 1 0 bank#1 0 1 bank#2 1 1 bank#3 address inputs: a0~a11 the a0~a11 inputs are address to access the memory cell array, as following table. row address column address tc59sm716as/asl a0~a11 a0~a8 tc59sm708as/asl a0~a11 a0~a9 tc59sm704as/asl a0~a11 a0~a9, a11 the row address bits are latched at the bank activate command and column address bits are latched on the read or write command. also, the a0~a11 inputs are used to set the data in the mode register in a mode register set cycle.
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 30/49 chip select: the cs input controls the latching of the commands on the positive edges of clk when cs is asserted ?low?. no commands are latched as long as cs is held ?high?. row address strobe: the ras input defines the operation commands in conjunction with the cas and we inputs, and is latched at the positive edges of clk. when ras and cs are asserted ?low? and cas is asserted ?high?, either the bank activate command or the precharge command is selected by the we signal. when we is asserted ?high?, the bank activate command is selected and the bank designated by bs0, bs1 are turned on so that it is in the active state. when we is asserted ?low?, the precharge command is selected and the bank designated by bs0, bs1 are switched to the idle state after precharge operation. column address strobe: the cas input defines the operation commands in conjunction with the ras and we inputs, and is latched at the positive edges of clk. when ras is held ?high? and cs is asserted ?low?, column access is started by asserting cas ?low?. then, the read or write command is selected by asserting we ?low? or ?high?. write enable: the we input defines the operation commands in conjunction with the ras and cas inputs, and is latched at the positive edges of clk. the we input is used to select the bank activate or precharge command and read or write command. data input/output mask: dqm or l-dqm and u-dqm the dqm input enables output in a read cycle and functions as the input data mask in a write cycle. when dqm is asserted ?high? at the positive edges of clk, output data is disabled after two clock cycles during a read cycle, and input data is masked at the same clock cycle during a write cycle. in the case of the tc59sm716as/asl, the ldqm and udqm inputs function as byte data control. the ldqm input can control dq0~dq7 in a read or write cycle and the udqm can control dq8~dq15 in a read or write cycle. data input/output: dq0~dq15 the dq0~dq15 input and output data are synchronized with the positive edges of clk. in the case of tc59sm708as/asl and tc59sm704as/asl, these pins are dq0~dq7 and dq0~dq3 respectively. cs ras cas we
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 31/49 operation mode table 1 shows the truth table for the operation commands. table 1. truth table (note (1) and (2) ) command device state cke n-1 cke n dqm (5) bs0, bs1 a10 a11, a9~a0 cs ras cas we bank activate idle (3) h x x v v v l l h h bank precharge any h x x v l x l l h l precharge all any h x x x h x l l h l write active (3) h x x v l v l h l l write with auto precharge active (3) h x x v h v l h l l read active (3) h x x v l v l h l h read with auto precharge active (3) h x x v h v l h l h mode register set idle h x x v v v l l l l no-operation any h x x x x x l h h h burst stop active (4) h x x x x x l h h l device deselect any h x x x x x h x x x auto-refresh idle h h x x x x l l l h self-refresh entry idle h l x x x x l l l h h x x x self-refresh exit idle (self refresh) l h x x x x l h h x clock suspend mode entry active h l x x x x x x x x h x x x power down mode entry idle/active (6) h l x x x x l h h x clock suspend mode exit active l h x x x x x x x x h x x x power down mode exit any (power down) l h x x x x l h h x data write/output enable active h x l x x x x x x x data write/output disable active h x h x x x x x x x note 1. v = valid, x = don?t care, l = low level, h = high level 2. cke n signal is input level when commands are issued. cke n-1 signal is input level one clock cycle before the commands are issued. 3. these are state designated by the bs0, bs1 signals. 4. device state is full page burst operation. 5. ldqm, udqm (tc59sm716as/asl) 6. power down mode can not entry in the burst cycle. when this command assert in the burst cycle, device state is clock suspend mode.
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 32/49 1. command function 1-1 bank activate command ( ras = l, cas = h, we = h, bs = bank, a0~a11 = row address) the bank activate command activates the bank designated by the bs (bank select) signal. row addresses are latched on a0~a11 when this command is issued and the cell data is read out to the sense amplifiers. the maximum time that each bank can be held in the active state is specified as t ras (max). 1-2 bank precharge command ( ras = l, cas = h, we = l, bs = bank, a10 = l, a0~a9, a11 = don?t care) the bank precharge command precharges the bank designated by bs. the precharged bank is switched from the active state to the idle state. 1-3 precharge all command ( ras = l, cas = h, we = l, bs = don?t care, a10 = h, a0~a9, a11 = don?t care) the precharge all command precharges all banks simultaneously. all banks are then switched to the idle state. 1-4 write command ( ras = h, cas = l, we = l, bs = bank, a10 = l, a0~a9, a11 = column address) the write command performs a write operation to the bank designated by bs. the write data is latched at the positive edges of clk. the length of the write data (burst length) and column access sequence (addressing mode) must be programmed in the mode resister at power-up prior to the write operation. the a11 input is ?don?t care? on the tc59sm708as/asl and the a9 and a11 inputs are ?don?t care? on the tc59sm716as/asl. 1-5 write with auto precharge command ( ras = h, cas = l, we = l, bs = bank, a10 = h, a0~a9, a11 = column address) the write with auto precharge command performs the precharge operation automatically after the write operation. the internal precharge starts in the cycles immediately following the cycle in which the last data is written independent of cas latency (figure 16). this command must not be interrupted by any other commands. the a11 input is ?don?t care? at the tc59sm708as/asl and the a9 and a11 inputs are ?don?t care? on the tc59sm716as/asl. 1-6 read command ( ras = h, cas = l, we = h, bs = bank, a10 = l, a0~a9, a11 = column address) the read command performs a read operation to the bank designated by bs. the read data is issued sequentially synchronized to the positive edges of clk. the length of read data (burst length), addressing mode and cas latency (access time from cas command in a clock cycle) must be programmed in the mode register at power-up prior to the write operation. the a11 input is ?don?t care? on the tc59sm708as/asl and the a9 and a11 inputs are ?don?t care? on the tc59sm716as/asl.
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 33/49 1-7 read with auto precharge command ( ras = h, cas = l, we = h, bs = bank, a10 = h, a0~a9, a11 = column address) the read with auto precharge command automatically performs the precharge operation after the read operation. when the cas latency = 3, the internal precharge starts two cycles before the last data is output. when the cas latency = 2, the internal precharge starts one cycle before the last data is output (figure 15). this command must not be interrupted by any other command. the a11 input is ?don?t care? on the tc59sm708as/asl and the a9 and a11 inputs are ?don?t care? on the tc59sm716as/asl. 1-8 mode register set command ( ras = l, cas = l, we = l, bs, a0~a11 = register data) the mode register set command programs the values of cas latency, addressing mode and burst length in the mode register. the default values in the mode register after power-up are undefined, therefore this command must be issued during the power-up sequence. also, this command can be issued while all banks are in the idle state. 1-9 no-operation command ( ras = h, cas = h, we = h) the no-operation command simply performs no operation. 1-10 burst stop command ( ras = h, cas = h, we = l) the burst stop command is used to stop the burst operation. this command is valid during a full page burst operation. during other types of burst operation, the command is illegal. 1-11 device deselect command ( cs = h) the device deselect command disables the command decoder so that the ras , cas , we and address inputs are ignored. this command is similar to the no-operation command. 1-12 auto refresh command ( ras = l, cas = l, we = h, cke = h, bs, a0~a11 = don?t care) the auto refresh command is used to refresh the row address provided by the internal refresh counter. the refresh operation must be performed 4096 times within 64 ms. the next command can be issued after t rc from the end of the auto refresh command. when the auto refresh command is issued, all banks must be in the idle state. the auto refresh operation is equivalent to the cas -before- ras operation in a conventional dram.
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 34/49 1-13 self refresh entry command ( ras = l, cas = l, we = h, cke = l, bs, a0~a11 = don?t care) the self refresh entry command is used to enter self refresh mode. while the device is in self refresh mode, all input and output buffers (except the cke buffer) are disabled and the refresh operation is automatically performed. self refresh mode is exited by taking cke ?high? (the self refresh exit command). 1-14 self refresh exit command (cke = h, cs = h or cke = h, ras = h, cas = h) this command is used to exit from self refresh mode. any subsequent commands can be issued after t rc from the end of this command. 1-15 clock suspend mode entry/power down mode entry command (cke = l) the internal clk is suspended for one cycle when this command is issued (when cke is asserted ?low?). the device state is held intact while the clk is suspended. on the other hand, when the device is not operating the burst cycle, this command performs entry into power down mode. all input and output buffers (except the cke buffer) are turned off in power down mode. 1-16 clock suspend mode exit/power down mode exit command (cke = h) when the internal clk has been suspended, operation of the internal clk is resumed by providing this command (asserting cke ?high?). when the device is in power down mode, the device exits this mode and all disabled buffers are turned on to the active state. any subsequent commands can be issued after one clock cycle from the end of this command. 1-17 data write/output enable, data mask/output disable command (dqm = l/h or ldqm, udqm = l/h) during a write cycle, the dqm or ldqm, udqm signal functions as data mask and can control every word of the input data. during a read cycle, the dqm or ldqm, udqm signal functions as the control of output buffers. the ldqm signal controls dq0~dq7 and the udqm signal controls dq8~dq15.
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 35/49 2. read operation issuing the bank activate command to the idle bank puts it into the active state. when the read command is issued after t rcd from the bank activate command, the data is read out sequentially, synchronized to the positive edges of clk (a burst read operation). the initial read data becomes available after cas latency from the issuing of the read command. the cas latency must be set in the mode register at power-up. in addition, the burst length of read data and addressing mode must be set. each bank is held in the active state unless the precharge command is issued, so that the sense amplifiers can be used as secondary cache. when the read with auto precharge command is issued, the precharge operation is performed automatically after the read cycle, then the bank is switched to the idle state. this command cannot be interrupted by any other commands. also, when the burst length is 1 and t rcd (min), the timing from the ras command to the start of the auto precharge operation is shorter than t ras (min). in this case, t ras (min) must be satisfied by extending t rcd (figure 9, 15). when the precharge operation is performed on a bank during a burst read operation, the burst operation is terminated (figure 20). when the burst length is full-page, column data is repeatedly read out until the burst stop command or precharge command is issued. 3. write operation issuing the write command after t rcd from the bank activate command, the input data is latched sequentially, synchronizing with the positive edges of clk after the write command (burst write operation). the burst length of the write data (burst length) and addressing mode must be set in the mode register at power-up. when the write with auto precharge command is issued, the precharge operation is performed automatically after the write cycle, then the bank is switched to the idle state. this command cannot be interrupted by any other command for the entire burst data duration. also, when the burst length is 1 and t rcd (min), the timing from the ras command to the start of the auto precharge operation is shorter than t ras (min). in this case, t ras (min) must be satisfied by extending t rcd (figure 10, 16). when the precharge operation is performed in a bank during a burst write operation, the burst operation is terminated (figure 20). when the burst length is full-page, the input data is repeatedly latched until the burst stop command or the precharge command is issued. when the burst read and single write mode is selected, the write burst length is 1 regardless of the read burst length.
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 36/49 4. precharge there are two commands which perform the precharge operation: bank precharge and precharge all. when the bank precharge command is issued to the active bank, the bank is precharged and then switched to the idle state. the bank precharge command can precharge one bank independently of the other bank and hold the unprecharged bank in the active state. the maximum time each bank can be held in the active state is specified as t ras (max). therefore, each bank must be precharged within t ras (max) from the bank activate command. the precharge all command can be used to precharge all banks simultaneously. even if banks are not in the active state, the precharge all command can still be issued. in this case, the precharge operation is performed only for the active bank and the precharged bank is then switched to the idle state. 5. page mode the read or write command can be issued on any clock cycle. whenever a read operation is to be interrupted by a write command, the output data must be masked by dqm to avoid i/o conflict. also, when a write operation is to be interrupted by a read command, only the input data before the read command is enable and the input data after the read command is disabled. 6. burst termination when the precharge command is issued for a bank in a burst cycle, the burst operation is terminated. when the burst read cycle is interrupted by the precharge command, read operation is disabled after clock cycle of ( cas latency-1) from the precharge command (figure 20). when the burst write cycle is interrupted by the precharge command, the input circuit is reset at the same clock cycle at which the precharge command is issued. in this case, the dqm signal must be asserted ?high? to prevent writing the invalid data to the cell array (figure 20). when the burst stop command is issued for the bank in a full-page burst cycle, the burst operation is terminated. when the burst stop command is issued during full-page burst read cycle, read operation is disabled after clock cycle of ( cas latency-1) from the burst stop command. when the burst stop command is issued during a full-page burst write cycle, write operation is disabled at the same clock cycle at which the burst stop command is issued. (figure 19)
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 37/49 7. mode register operation the mode register designates the operation mode for the read or write cycle. this register is divided into three fields; a burst length field to set the length of burst data, an addressing mode selected bits to designate the column access sequence in a burst cycle, and a latency field to set the access time in clock cycle. the mode register is programmed by the mode register set command when all banks are in the idle state. the data to be set in the mode register is transferred using the a0~a11, bs0, bs1 address inputs. the initial value of the mode register after power-up is undefined; therefore the mode register set command must be issued before proper operation. ? burst length field (a2~a0) this field specifies the data length for column access using the a2~a0 pins and sets the burst length to be 1, 2, 4, 8, words, or full-page. a2 a1 a0 burst length 0 0 0 1 word 0 0 1 2 words 0 1 0 4 words 0 1 1 8 words 1 1 1 full-page ? addressing mode select (a3) the addressing mode can be one of two modes; interleave mode or sequential mode. when the a3 bit is 0, sequential mode is selected. when the a3 bit is 1, interleave mode is selected. both addressing modes support burst length of 1, 2, 4 and 8 words. additionally, sequential mode supports the full-page burst. a3 addressing mode 0 sequential 1 interleave cas
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 38/49 ? addressing sequence of sequential mode a column access is performed by incrementing the column address input to the device. the address is varied by the burst length as shown in table 2. table 2. addressing sequence for sequential mode data access address burst length data0 n data1 n + 1 data2 n + 2 data3 n + 3 data4 n + 4 data5 n + 5 data6 n + 6 data7 n + 7 2 words (address bits is a0) not carried from a0 to a1 4 words (address bits is a1, a0) not carried from a1 to a2 8 words (address bits is a2, a1, a0) not carried from a2 to a3 ? addressing sequence of interleave mode a column access is started from the input column address and is performed by inverting the address bits in the sequence shown in table 3. table 3. addressing sequence for interleave mode data access address burst length data0 a8 a7 a6 a5 a4 a3 a2 a1 a0 data1 a8 a7 a6 a5 a4 a3 a2 a1 0 a data2 a8 a7 a6 a5 a4 a3 a2 1 a a0 data3 a8 a7 a6 a5 a4 a3 a2 1 a 0 a data4 a8 a7 a6 a5 a4 a3 2 a a1 a0 data5 a8 a7 a6 a5 a4 a3 2 a a1 0 a data6 a8 a7 a6 a5 a4 a3 2 a 1 a a0 data7 a8 a7 a6 a5 a4 a3 2 a 1 a 0 a 2 words 4 words 8 words
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 39/49 addressing sequence example (burst length = 8 and input address is 13.) interleave mode sequential mode data a8 a7 a6 a5 a4 a3 a2 a1 a0 add add data0 0 0 0 0 0 1 1 0 1 13 13 13 data1 0 0 0 0 0 1 1 0 0 12 13 + 1 14 data2 0 0 0 0 0 1 1 1 1 15 13 + 2 15 data3 0 0 0 0 0 1 1 1 0 14 13 + 3 8 data4 0 0 0 0 0 1 0 0 1 9 13 + 4 9 data5 0 0 0 0 0 1 0 0 0 8 13 + 5 10 data6 0 0 0 0 0 1 0 1 1 11 13 + 6 11 data7 0 0 0 0 0 1 0 1 0 10 13 + 7 12 calculated using a2, a1 and a0 bits not carry from a2 to a3 bit. ? cas latency field (a6~a4) this field specifies the number of clock cycles from the assertion of the read command to the first data read. the minimum values of cas latency depends on the frequency of clk. the minimum value must be set in this field. a6 a5 a4 cas latency 0 1 0 2 clock 0 1 1 3 clock ? test mode entry bit (a7) this bit is used to enter test mode and must be set to 0 for normal operation. ? reserved bits (a8, a10, a11, bs0, bs1) these bits are reserved for future operations. they must be set to 0 for normal operation. ? single write mode (a9) this bit is used to select the write mode. when the a9 bit is 0, burst read and burst write mode are selected. when the a9 bit is 1, burst read and single write mode are selected. a9 write mode 0 burst read and burst write 1 burst read and single write read cycle cas latency = 3 command read 13 0 1 2 3 4 5 6 7 8 9 10 11 dq0~dq7 q0 q1 q2 q3 q4 q5 q6 q7 address data address interleave mode 13 12 15 14 9 8 11 10 13 14 15 8 9 10 11 12 sequential mode
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 40/49 8. refresh operation two types of refresh operation can be performed on the device: auto refresh and self refresh. auto refresh is similar to the cas -before- ras refresh of conventional drams and is performed by issuing the auto refresh command while all banks are in the idle state. by repeating the auto refresh cycle, each bank refreshed automatically. the refresh operation must be performed 4096 times (rows) within 64 ms (figure 11). the period between the auto refresh command and the next command is specified by t rc . self refresh mode is entered by issuing the self refresh command (cke asserted ?low?) while all banks are in the idle state. the device is in self refresh mode for as long as cke is held ?low?. in self refresh mode, all input/output buffers (except the cke buffer) are disabled to lower power dissipation (figure 12). in the case of 4096 burst auto refresh commands, 4096 burst auto refresh commands must be performed within 15.6 s before entering and after exiting the self refresh mode. in the case of distributed auto refresh commands, distributed auto refresh commands must be issued every 15.6 s and the last distributed auto refresh command must be performed within 15.6 s before entering the self refresh mode. after exiting from the self refresh mode, the refresh operation must be performed within 15.6 s. 9. power down mode when the device enters the power down mode, all input/output buffers (except cke buffer) are disabled to lower power dissipation in the idle state. power down mode is entered by asserting cke ?low? while the device is not running a burst cycle. taking cke ?high? exit this mode. when cke goes high, a no-operation command must be input at next clk rising edge of clk (figure 13) and cke should be set high at least 1clk + t cks at power down mode exit. 10. clk suspension and input/output mask when the device is running a burst cycle, the internal clk is suspended by asserting cke ?low? and the burst operation is frozen from the next cycle. a read/write operation is held intact until the cke signal is taken ?high?. the output disable/write mask signal (dqm) has two functions, controlling the output data in a read cycle and performing word mask in a write cycle. when the dqm is asserted ?high? at the positive edge of clk, the output data is disabled after two clock cycles in the case of a read operation and the write data is masked at the same clock cycle in the case of a write operation. the timing relations between the cke timing and dqm are described in figure 21 (a) and 21 (b).
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 41/49 figure 15. auto precharge timing (read cycle) (1) cas latency = 2 (a) burst length = 1 command read dq ap act q0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 t rp (b) burst length = 2 command dq (c) burst length = 4 command dq (d) burst length = 8 command dq (2) cas latency = 3 (a) burst length = 1 command dq (b) burst length = 2 command dq (c) burst length = 4 command dq (d) burst length = 8 command dq read ap act q0 read ap act q0 read q0 read ap act q0 t rp read ap act q0 t rp read ap act q0 t rp read ap act t rp q0 q1 q1 q2 q3 ap act q1 q2 q3 q4 q5 q6 q7 q1 q1 q2 q3 q1 q2 q3 q4 q5 q6 q7 note) ? represents the read with auto precharge command. ? represents the start of internal precharging. ? represents the bank activate command. ? when the auto precharge command is asserted, the period from the bank activate command to the start of internal precharging must be at least t ras (min). read ap act t rp t rp t rp
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 42/49 figure 16. auto precharge timing (write cycle) (1) cas latency = 2 (a) burst length = 1 command write dq ap act d0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 t rp (b) burst length = 2 command dq (c) burst length = 4 command dq (d) burst length = 8 command dq (2) cas latency = 3 (a) burst length = 1 command dq (b) burst length = 2 command dq (c) burst length = 4 command dq (d) burst length = 8 command dq write ap act d0 write ap act d0 write d0 write ap act d0 t rp write ap act d0 t rp write ap act d0 t rp write ap act t rp d0 d1 d1 d2 d3 ap act d1 d2 d3 d4 d5 d6 d7 d1 d1 d2 d3 d1 d2 d3 d4 d5 d6 d7 t wr t wr t wr t wr t wr t wr t wr t wr note) ? represents the write with auto precharge command. ? represents the start of internal precharging. ? represents the bank activate command. ? when the auto precharge command is asserted, the period from the bank activate command to the start of internal precharging must be at least t ras (min). write ap act t rp t rp t rp
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 43/49 figure 17. timing chart for read-to-write cycle (1) cas latency = 2 (a) command read dq write d0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 d1 d2 d3 dqm in the case of burst length = 4 (b) command read dq write d0 d1 d2 d3 dqm (2) cas latency = 3 (a) command read dq write d0 d1 d2 d3 dqm (b) command read dq write d0 d1 d2 d3 dqm note) ? the output data must be masked by dqm to avoid i/o conflict.
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 44/49 figure 18. timing chart for write-to-read cycle (1) cas latency = 2 (a) command read dq write q0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 q1 q2 q3 dqm in the case of burst length = 4 (b) command read dq write d0 d1 dqm (2) cas latency = 3 (a) command read dq write dqm (b) command read dq write dqm d0 q0 q1 q2 q3 q0 q1 q2 q3 d0 d0 d1 q0 q1 q2 q3
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 45/49 figure 19. timing chart for burst stop cycle (burst stop command) dq bst q0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 q1 q2 q3 (1) read cycle (a) cas latency = 2 command read dq bst (b) cas latency = 3 command bst dq write (2) write cycle command read q4 q0 q1 q2 q3 q4 d0 d1 d2 d3 d4 note) ? represents the burst stop command. bst
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 46/49 figure 20. timing chart for burst stop cycle (precharge command) dq prcg q0 0 1 2 3 4 5 6 7 8 9 10 11 12 q1 q2 q3 (1) read cycle (a) cas latency = 2 command read dq prcg (b) cas latency = 3 command prcg write command read q4 q0 q1 q2 q3 q4 (2) write cycle (a) cas latency = 2 prcg dqm write command d1 d2 d3 d4 (b) cas latency = 3 dq d0 t wr note) ? represents the precharge command. prcg dq d0 d1 d2 d3 d4 dqm t wr in the case of burst length = 8
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 47/49 figure 21 (a). cke/dqm input timing (write cycle) (1) 1 2 3 4 5 6 7 dq dqm cke external clk cycle no. internal clk d1 dqm mask cke mask d2 d3 d5 d6 (3) 1 2 3 4 5 6 7 dq dqm cke clk cycle no. d1 cke mask d2 d3 d5 d6 d4 (2) 1 2 3 4 5 6 7 dq dqm cke clk cycle no. d1 dqm mask cke mask d2 d3 d5 d6 external internal clk external internal clk
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 48/49 figure 21 (b). cke/dqm input timing (read cycle) (1) 1 2 3 4 5 6 7 dq dqm cke external clk cycle no. internal clk q1 q2 q3 q6 (3) 1 2 3 4 5 6 7 dq dqm cke clk cycle no. q1 q2 q4 q5 q6 (2) 1 2 3 4 5 6 7 dq dqm cke clk cycle no. q1 q2 q3 q6 q4 open open q4 open q3 external internal clk external internal clk
tc59sm716/08/04as/asl-70,-75,-80 2001-06-11 49/49 package dimensions unit: mm

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